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? semiconductor components industries, llc, 2006 august, 2006 ? rev. 3 1 publication order number: ncp1522/d ncp1522 3.0 mhz, 600 ma, high?efficiency, low quiescent current, adjustable output voltage step?down converter the ncp1522 step?down pwm dc?dc converter is optimized for portable applications powered from one cell li?ion or three cell alkaline/nicd/nimh batteries. the device is available in an adjustable output voltage from 0.9 v to 3.3 v. it uses synchronous rectification to increase efficiency and reduce external part count. the device also has a built?in 3.0 mhz (nominal) oscillator which reduces component size by allowing a small inductor and capacitors. automatic switching pwm/pfm mode offers improved system efficiency. finally, it includes an integrated soft?start, cycle?by?cycle current limiting, and thermal shutdown protection. the ncp1522 is available in a space saving, low profile tsop5 package. features ? 93.8% of efficiency for 3.3 v output and 4.5 v input and 120 ma load current ? sources up to 600 ma ? 3.0 mhz switching frequency ? adjustable output voltage from 0.9 v to 3.3 v ? 60 a quiescent current (typ) ? synchronous rectification for higher efficiency ? 2.7 v to 5.5 v input voltage range ? thermal limit protection ? shutdown current consumption of 0.3 a ? short circuit protection ? this is a pb?free device typical applications ? cellular phones, smart phones and pdas ? mp3 players and portable audio systems ? wireless and dsl modems ? portable equipment ? usb powered devices ? digital still/video cameras gnd 2 vin 1 en 3 lx 5 fb 4 off on vin cin cout r1 r2 cff figure 1. typical application l vout tsop?5 asn suffix case 483 pin connections device package shipping ordering information NCP1522ASNT1G tsop?5 (pb?free) 3000/t ape & ree l http://onsemi.com marking diagram a = assembly location y = year w = work week = pb?free package (note: microdot may be in either location ) (top view) 1 5 1 5 dbrayw 1 2 3 5 4 vin gnd en lx fb ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d.
ncp1522 http://onsemi.com 2 v out = 3.3 v v in = 4.5 v t a = 25 c 100 90 80 70 60 50 500 600 400 300 200 100 0 i out (ma) eff (%) figure 2. efficiency vs. output current gnd 2 vin 1 vbattery 4.7 f en 3 enable logic control & thermal shutdown pwm/burst control ilimit reference voltage fb 4 lx 5 q1 4.7 f 18 pf r1 r2 2.2 h q2 figure 3. simplified block diagram
ncp1522 http://onsemi.com 3 pin function description pin no. symbol function description 1 vin analog input power supply input for analog v cc . 2 gnd analog/power ground ground connection for the nfet power stage and the analog sections of the ic. 3 en digital input enable for switching regulator. this pin is active high. do not float this pin. 4 fb analog input feedback voltage from the output of the power supply. this is the input to the error amplifier. 5 lx analog output connection from power mosfets to the inductor. for one option, an output discharge circuit sinks current from this pin. maximum ratings rating symbol value unit minimum voltage all pins v min ?0.3 v maximum voltage all pins (note 1) v max 7.0 v maximum voltage enable, fb, lx v max vin + 0.3 v thermal resistance, junction ?to?air r ja 200 c/w operating ambient temperature range t a ?40 to 85 c storage temperature range t stg ?55 to 150 c junction operating temperature t j ?40 to 125 c latch?up current maximum rating (t a = 85 c) (note 2) lu +/?100 ma esd withstand voltage (note 3) human body model machine model vesd 2.0 200 kv v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. according to jedec standard jesd22?a108b. 2. latchup current maximum rating per jedec standard: jesd78. 3. this device series contains esd protection and exceeds the following tests: human body model (hbm) per jedec standard: jesd22?a114. machine model (mm) per jedec standard: jesd22?a115.
ncp1522 http://onsemi.com 4 electrical characteristics (typical values are referenced to t a = +25 c, min and max values are referenced ?40 c to +85 c ambient temperature, unless otherwise noted, operating conditions v in = 3.6 v, v out = 1.8 v, unless otherwise noted.) characteristic symbol min typ max unit input voltage range v in 2.7 ? 5.5 v undervoltage lockout (v in falling) v uvlo 2.3 2.5 2.6 v quiescent current (pfm no load) i q ? 60 95 a standby current, en low istb ? 0.3 1.2 a oscillator frequency f osc 2.400 3.0 3.600 mhz peak inductor current i lim ? 1200 ? ma feedback re ference voltage v ref ? 0.6 ? v fb pin tolerance vfbtol ?3.0 ? 3.0 % reference voltage line regulation vfb ? 0.1 ? % output voltage accuracy (note 4) v out ?3% vnom +3% v minimum output v oltage v out ? 0.9 ? v maximum output voltage v out ? 3.3 ? v output voltage line regulation (v in = 2.7?5.5) io = 200 ma v out ? 0.1 ? % voltage load regulation (io = 200 ma to 300 ma) (io = 200 ma to 600 ma) v loadreg ? ? 0.0005 0.001 ? ? %/ma %/ma load transient response (300 ma to 600 ma load step, trise 1.0 s) v out ? 35 ? mv duty cycle ? ? ? 100 % p?ch on?resistance rlxh ? 300 ? m n?ch on?resistance rlxl ? 300 ? m p?ch leakage current ileakh ? 0.05 ? a n?ch leakage current ileakl ? 0.01 ? a enable pin high venh 1.2 ? ? v enable pin low venl ? ? 0.4 v en << h >> input current, en = 3.6 v ienh ? 2.0 ? a soft?start time t start ? 350 500 s thermal shutdown threshold t sd ? 160 ? c thermal shutdown hysteresis t sdh ? 25 ? c 4. the overall output voltage tolerance depends upon the accuracy of the external resistor (r1, r2).
ncp1522 http://onsemi.com 5 figure 4. quiescent current vs. supply voltage figure 5. quiescent cu rrent vs. temperature figure 6. shutdown current vs. supply voltage figure 7. efficiency vs. output current (v out = 1.8 v, v in = 3.6 v) figure 8. efficiency vs. output current (v out = 0.9 v, v in = 3.6 v) figure 9. efficiency vs. output current (v out = 3.3 v, v in = 4.5 v) 0 i out , output current (ma) 100 90 70 100 200 300 400 500 600 80 75 efficiency (%) efficiency (%) 60 0 100 200 300 400 500 i out , output current (ma) 50 quiescent current ( a) v in , input voltage (v) 0 10 20 30 40 50 2.7 3.2 3.7 4.2 4.7 shutdown current ( a) 2.7 3.2 4.7 1.0 0.6 0.4 0.2 0 v in , input voltage (v) 3.7 600 en = v in i out = 0 ma 5.2 5.7 t a = 25 c 100 80 70 90 60 70 80 90 100 quiescent current ( a) temperature ( c) 0 10 20 30 40 50 ?40 ?20 0 20 40 v in = 5.5 v 60 100 60 70 80 90 100 v in = 2.7 v 80 0.8 4.2 en = 0 v i out = 0 ma 95 85 t a = 85 c t a = ?40 c t a = 25 c t a = 85 c t a = ?40 c efficiency (%) 0 100 200 300 400 500 i out , output current (ma) 600 100 80 70 90 t a = 25 c t a = 85 c t a = ?40 c
ncp1522 http://onsemi.com 6 figure 10. efficiency vs. output current (v in = 4.0 v) figure 11. frequency vs. input voltage figure 12. frequency vs. temperature figure 13. load regulation figure 14. output voltage vs. enable input pin voltage figure 15. pfm/pwm threshold vs. input voltage 0 i out , output current (ma) 3.0 1.0 ?3.0 100 200 300 400 500 700 ?1.0 ?2.0 load regulation (%) output voltage (v) 0.5 0 0.2 0.4 0.6 0.8 1.0 v in , enable input voltage (v) 0.0 1.4 1.5 1.0 2.0 frequency (mhz) v in , input voltage (v) 2.4 2.6 2.8 3.0 3.2 3.4 2.7 3.2 3.7 4.2 4.7 5.7 3.6 5.2 2.0 0.0 output current (ma) 2.7 3.2 3.7 4.2 4.7 5.2 v in , input voltage (v) 5.7 300 100 0 200 0 i out , output current (ma) 100 80 30 100 200 300 400 500 600 60 50 efficiency (%) 90 70 v out = 3.3 v v out = 1.8 v 40 v out = 0.9 v i out = 300 ma i out = 600 ma frequency (mhz) temperature ( c) 2.4 2.6 2.8 3.0 3.2 3.4 ?40 ?20 0 20 40 100 3.6 60 v in = 5.5 v i out = 300 ma 80 v in = 3.6 v 1.5 ?2.5 ?0.5 ?1.5 2.5 0.5 600 v out = 3.3 v v out = 1.8 v v out = 0.9 v 1.2 250 50 150 v out = 1.8 v t a = 25 c
ncp1522 http://onsemi.com 7 figure 16. output voltage accuracy (v out = 0.9 v) figure 17. output voltage accuracy (v out = 1.8 v) figure 18. output voltage accuracy (v out = 3.3 v) ?50 temperature ( c) 1.0 0 50 100 150 ?1.0 ?2.0 output voltage (%) 2.0 0.0 1.5 ?0.5 ?1.5 0.5 i out = 600 ma i out = 300 ma i out = 100 ma ?50 temperature ( c) 1.0 0 50 100 150 ?1.0 ?2.0 output voltage (%) 2.0 0.0 1.5 ?0.5 ?1.5 0.5 i out = 600 ma i out = 300 ma i out = 100 ma ?50 temperature ( c) 1.0 0 50 100 150 ?1.0 ?2.0 output voltage (%) 2.0 0.0 1.5 ?0.5 ?1.5 0.5 i out = 600 ma i out = 300 ma i out = 100 ma v in = 3.6 v v in = 3.6 v v in = 4.0 v
ncp1522 http://onsemi.com 8 figure 19. load transient response in pwm operation (v in = 3.6 v) figure 20. load transient response in pwm operation (v in = 3.6 v) figure 21. soft start time (v in = 3.6 v) figure 22. short circuit protection (v in = 3.6 v) i out 200 ma/div v out 20 mv/div 10 s/div i out 200 ma/div v out 20 mv/div 10 s/div en 2 v/div v out 500 mv/div 100 s/div v out 500 mv/div 2.5 s/div i lx 500 ma/div
ncp1522 http://onsemi.com 9 operation description overview the ncp1522 uses a constant frequency, voltage mode step?down architecture. both the main (p?channel mosfet) and synchronous (n?channel mosfet) switches are internal. it delivers a constant voltage from either a single li?ion or three cell nimh/nicd battery to portable devices such as cell phones and pda. the output voltage is set by external resistor divider. the ncp1522 sources at least 600 ma depending on external components chosen. the ncp1522 works with two modes of operation; pwm depending on the current required. the device operates in pwm/pfm mode at load currents of approximately 80 ma or higher, having voltage tolerance of 3% with 90% efficiency or better. lighter load currents cause the device to automatically switch into pfm mode for reduced current consumption (i q = 60 a typ) and extended battery life. additional features include soft?start, undervoltage protection, current overload protection, and thermal shutdown protection. as shown in figure 1, only six external components are required for implementation. the part uses an internal reference voltage of 0.6 v. it is recommended to keep the part in shutdown until the input voltage is 2.7 v or higher. pwm operating mode in this mode, the output voltage of the ncp1522 is regulated by modulating the on?time pulse width of the main switch q1 at a fixed frequency of 3.0 mhz. the switching of the pmos q1 is controlled by a flip?flop driven by the internal oscillator and a comparator that compares the error signal from an error amplifier with the pwm ramp. at the beginning of each cycle, the main switch q1 is turned on by the rising edge of the internal oscillator clock. the inductor current ramps up until the sum of the current sense signal and compensation ramp becomes higher than the error voltage amplifier. once this has occurred, the pwm comparator resets the flip?flop, q1 is turned off and the synchronous switch q2 is turned on. q2 replaces the external schottky diode to reduce the conduction loss and improve the efficiency. to avoid overall power loss, a certain amount of dead time is introduced to ensure q1 is completely turned off before q2 is being turned on. figure 23. pwm switching w aveform (v in = 3.6 v, v out = 1.8 v, i out = 300 ma) 125 ns/div pfm operating mode under light load conditions, the ncp1522 enters in low current pfm mode operation to reduce power consumption. the output regulation is implemented by pulse frequency modulation. if the output voltage drops below the threshold of pfm comparator (typically vnom?2%), a new cycle will be initiated by the pfm comparator to turn on the switch q1. q1 remains on until the peak inductor current reaches 200 ma (nom). then i lim comparator goes high to switch off q1. after a short dead time delay, switch rectifier q2 is turned on. the negative current detector (ncd) will detect when the inductor current drops below zero and sends the signal to turn off q2. the output voltage continues to decrease through discharging the output capacitor. when the output voltage falls below the threshold of the pfm comparator, a new cycle starts immediately. figure 24. pfm mode switching waveform (v in = 3.6 v, v out = 1.8 v, i out = 30 ma) 5 s/div
ncp1522 http://onsemi.com 10 cycle?by?cycle current limitation from the block diagram (figure 3), an i lim comparator is used to realize cycle?by?cycle current limit protection. the comparator compares the lx pin voltage with the reference voltage, which is biased by a constant current. if the inductor current reaches the limit, the i lim comparator detects the lx voltage falling below the reference voltage and releases the signal to turn off the switch q1. the cycle?by?cycle current limit is set at 1200 ma (nom). short circuit protection when the output is shorted to ground, the device limits the inductor current. the duty?cycle is minimum and the consumption on the input line is 300 ma (typ). when the short circuit condition is removed, the device returns to the normal mode of operation. soft?start the ncp1522 uses soft?start (300 s typ) to limit the inrush current when the device is initially enabled. soft?start is implemented by gradually increasing the reference voltage until it reaches the full reference voltage. during startup, a pulsed current source charges the internal soft?start capacitor to provide gradually increasing reference voltage. when the voltage across the capacitor ramps up to the nominal reference voltage, the pulsed current source will be switched off and the reference voltage will switch to the regular reference voltage. shutdown mode when the en pin has a voltage applied of less than 0.4 v, the ncp1522 will be disabled. in shutdown mode, the internal reference, oscillator and most of the control circuitries are turned off. therefore, the typical current consumption will be 0.3 a (typical value). applying a voltage above 1.2 v to en pin will enable the device for normal operation. the device will go through soft?start to normal operation, however, the en pin should be tied low while the input voltage on v in pin is rising up. thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. if the junction temperature exceeds 160 c, the device shuts down. in this mode switch q1 and q2 and the control circuits are all turned off. the device restarts in soft?start after the temperature drops below 135 c. this feature is provided to prevent catastrophic failures from accidental device overheating and it is not intended as a substitute for proper heatsinking. low dropout operation the ncp1522 offers a low input to output voltage difference. the ncp1522 can operate at 100% duty cycle. in this mode the pmos (q1) switches completely on. the minimum input voltage to maintain regulation can be calculated as: v in(min) v out(max) (eq. 1) (i out (r ds(on) r inductor )) ? v out : output voltage (volts) ? i out : max output current ? r ds(on) : p?channel switch r ds(on) ? r inductor : inductor resistance (dcr)
ncp1522 http://onsemi.com 11 application information output voltage selection the output voltage is programmed through an external resistor divider connected from v out to fb then to gnd. for low power consumption and noise immunity, the resistor from fb to gnd (r2) should be in the [100 k?600 k] range. if r2 is 200 k given the v fb is 0.6 v, the current through the divider will be 3.0 a. the formula below gives the value of v out , given the desired r1 and the r1 value: v out v fb (1 r1 r2 ) (eq. 2) ? v out : output voltage (volts) ? v fb : feedback voltage = 0.6 v ? r1: feedback resistor from v out to fb ? r2: feedback resistor from fb to gnd input capacitor selection in pwm operating mode, the input current is pulsating with large switching noise. using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. the capacitance needed for the input bypass capacitor depends on the source impedance of the input supply. the maximum rms current occurs at 50% duty cycle with maximum output current, which is io, max/2. for ncp1522, a low profile, low esr ceramic capacitor of 4.7 f should be used for most of the cases. for ef fective bypass results, the input capacitor should be placed as close as possible to the v in pin. table 1. list of input capacitor murata grm188r60j475ke grm21br71c475ka taiyo yuden jmk212by475mg tdk c2012x5roj475kb c1632x5roj475kt output l?c filter design considerations the ncp1522 is built in 3.0 mhz frequency and uses voltage mode architecture. the correct selection of the output filter ensures good stability and fast transient response. due to the nature of the buck converter, the output l?c filter must be selected to work with internal compensation. for ncp1522, the internal compensation is internally fixed and it is optimized for an output filter of l = 2.2 h and c out = 4.7 f. the corner frequency is given by: f c 1 2 l c out (eq. 3) 1 2 2.2 h 4.7 f 49.5 khz the device is intended to operate with inductance between 1.0 h and maximum of 4.7 h. if the corner frequency is moved, it is recommended to check the loop stability depending on the output ripple voltage accepted and output current required. for lower frequency, the stability will be increased; a larger output capacitor value could be chosen without critical effect on the system. on the other hand, a smaller capacitor value increases the corner frequency and it should be critical for the system stability. take care to check the loop stability. the phase margin is usually higher than 45 . table 2. l?c filter example inductance (l) output capacitor (c out ) 1.0 h 10 f 2.2 h 4.7 f 4.7 h 2.2 f inductor selection the inductor parameters directly related to device performances are saturation current and dc resistance and inductance value. the inductor ripple current (?i l ) decreases with higher inductance: i l v out l f sw 1? v out v in (eq. 4) i l peak to peak inductor ripple current l inductor value f sw switching frequency the saturation current of the inductor should be rated higher than the maximum load current plus half the ripple current: i l(max) i o(max) i l 2 (eq. 5) i l(max) maximum inductor current i o(max) maximum output current the inductor?s resistance will factor into the overall efficiency of the converter. for best performances, the dc resistance should be less than 0.3 for good efficiency.
ncp1522 http://onsemi.com 12 table 3. list of inductor fdk mipw3226 series tdk vlf3010at series taiyo yuden lq cbl2012 coil craft do1605?t series lpo3010 output capacitor selection selecting the proper output capacitor is based on the desired output ripple voltage. ceramic capacitors with low esr values will have the lowest output ripple voltage and are strongly recommended. the output capacitor requires either an x7r or x5r dielectric. the output ripple voltage in pwm mode is given by: v out i l 1 4 f sw ?3 c out esr (eq. 6) in pfm mode (at light load), the output voltage is regulated by pulse frequency modulation. the output voltage ripple is independent of the output capacitor value. it is set by the threshold of pfm comparator. table 4. list of output capacitor murata grm188r60j475ke 4.7 f grm21br60j106me19l 10 f grm188r60oj106me 10 f taiyo yuden jmk212by475mg 4.7 f jmk212bj106mg 10 f tdk c2012x5roj475kb 4.7 f c1632x5roj475kt 4.7 f c2012x5roj106k 10 f feed?forward capacitor selection the feed?forward capacitor sets the feedback loop response and is critical to obtain good loop stability. given that the compensation is internally fixed, an 18 pf or higher ceramic capacitor is needed. choose a small ceramic capacitor x7r or x5r or cog dielectric.
ncp1522 http://onsemi.com 13 application board pcb layout recommendations good pcb layout plays an important role in switching mode power conversion. careful pcb layout can help to minimize ground bounce, emi noise and unwanted feedback that can affect the performance of the converter. hints suggested below can be used as a guideline in most situations. 1. use star?ground connection to connect the ic ground nodes and capacitor gnd nodes together at one point. keep them as close as possible, and then connect this to the ground plane through several vias. this will reduce noise in the ground plane by preventing the switching currents from flowing through the ground plane. 2. place the power components (i.e., input capacitor, inductor and output capacitor) as close together as possible for best performance. all connecting traces must be short, direct, and wide to reduce voltage errors caused by resistive losses through the traces. 3. separate the feedback path of the output voltage from the power path. keep this path close to the ncp1522 circuit. and also route it away from noisy components. this will prevent noise from coupling into the voltage feedback trace. 4. place the dc?dc converter away from noise sensitive circuitry, such as rf circuits. the following shows the ncp1522 demo board schematic, layout, and bill of materials: gnd 2 vin 1 en 3 lx 5 fb 4 off on vin cin cout r1 r2 cff l vout figure 25. ncp1522 board schematic figure 26. ncp1522 board layout
ncp1522 http://onsemi.com 14 j1 1 2 0 power c1 4.7 f vin vfvin 0 1 2 3 en u1 vp gnd en fb lx 5 4 lx 1 ncp152x 0 2 c2 4.7 f r1 220 r r2 220 r 0 c3 18 pf vout 0 1 2 output j3 vp 1 2 3 con3 j5 r3 220 k 0 en 0 bnch j4 figure 27. schematics 2.2 h l1 figure 28. silkscreen layer
ncp1522 http://onsemi.com 15 figure 29. board layout (top view) figure 30. board layout (bottom view)
ncp1522 http://onsemi.com 16 bill of materials item part description ref pcb footprint manufacturer manufacturer reference 1 ncp1522 dc?dc converter u1 tsop?5 on semiconductor ncp1522 2 4.7 f ceramic capacitor 6.3 v x5r c1, c2 0805 murata grm21 series 3 18 pf ceramic capacitor 50 v cog c3 0603 murata grm188 series 4 smd resistor 220 k r1, r2, r3 0805 vishay?draloric crcw0805 5 smd inductor l1 1605 coilcraft do1605 series 6 i/o connector can be plugged by blz5.08/2 (weidmller reference) j1, j3 ? weidmller sl5.08/2/90b 7 jumper header vertical mount 3*1, 2.54 mm j5 ? tyco electronics/amp 5?826629?0 8 jumper connector, 400 mils j6, j7 ? harwin d3082?b01
ncp1522 http://onsemi.com 17 package dimensions tsop?5 sn suffix case 483?02 issue f notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. 5. optional construction: an additional trimmed lead is allowed in this location. trimmed lead not to extend more than 0.2 from body. dim min max millimeters a 3.00 bsc b 1.50 bsc c 0.90 1.10 d 0.25 0.50 g 0.95 bsc h 0.01 0.10 j 0.10 0.26 k 0.20 0.60 l 1.25 1.55 m 0 10 s 2.50 3.00 123 54 s a g l b d h c j 0.7 0.028 1.0 0.039 mm inches scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 0.20 5x c ab t 0.10 2x 2x t 0.20 note 5 t seating plane 0.05 k m detail z detail z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ncp1522/d publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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